Dynamic Power Partitioning and Control for Performance Optimization in Chip Multiprocessors

Since power consumption has become a major constraint for the further throughput improvement of chip multiprocessors (CMPs), a key challenge is to optimize the performance of a CMP within a power budget limited by the CMP’s cooling, packaging, and power supply capacities. Most existing solutions rely solely on dynamic voltage and frequency scaling (DVFS) to adapt the power consumption of CPU cores, without coordinating with on-chip L2 caches. However, dynamic cache resizing can be adopted to put rarely accessed cache ways into low-power modes, allowing power to be shifted to the CPU cores for improved performance. In this paper, we propose a novel chip-level power control strategy that can dynamically shift power among the CPU cores and shared L2 caches in a CMP based on the workload characteristics measured online, while maintaining the total power of the CMP below a given budget. Specifically, we implement an online model estimator to dynamically measure the performance contributed by each core and the shared caches and then use linear programming to optimally partition the chip-level power budget among them. We then design power control algorithms based on feedback control theory for CPU cores and caches such that their power consumption is controlled to their respective local budgets. We compare our solution with several state-of-the-art power control solutions. Our extensive experimental results demonstrate that our solution achieves 10.2% better performance on average, in terms of instructions per cycle (IPC), than the best-performing baseline.